Instruction Level Energy Modeling for Pipelined Processors
نویسندگان
چکیده
A new method for creating instruction level energy models for pipelined processors is introduced. This method is based on measuring the instantaneous current drawn by the processor during the execution of the instructions. An appropriate instrumentation set up was established for this purpose. According to the proposed method the energy costs (base and inter-instruction costs) are modeled in relation to a reference instruction (e.g. NOP). These costs incorporate inter-cycle energy components, which cancel each other when they are summed to produce the energy consumption of a program resulting in estimates with high accuracy. This is confirmed by the results. Also the dependencies of the energy consumption on the instruction parameters (e.g. operands, addresses) are studied and modeled in an efficient way.
منابع مشابه
Superscalar instruction issue
learly, instruction issue and execution are closely related: The more parallel the instruction execution, the higher the requirements for the parallelism of instruction issue. Thus, we see the continuous and harmonized increase of parallelism in instruction issue and execution. This article focuses on superscalar instruction issue, tracing the way parallel instruction execution and issue have i...
متن کاملSynthesizable HDL Generation for Pipelined Processors from a Micro-Operation Description
A synthesizable HDL generation method for pipelined processors is proposed. By using the proposed method, data-path and control logic descriptions of a target processor is generated from a clock based instruction set specification. From the experimental results, feasibility of the proposed method is evaluated and the amount of processor design time was drastically reduced than that of conventio...
متن کاملVerification of in-order execution in pipelined processors
As embedded systems continue to face increasingly higher performance requirements, deeply pipelined processor architectures are being employed to meet desired system performance. System architects critically need modeling techniques that allow exploration, evaluation, customization and validation of different processor pipeline configurations, tuned for a specific application domain. We propose...
متن کاملVHDL Token-based Performance Modeling for 2D and 3D Infrared Search and Track Processing
The purpose of this study was to develop and evaluate a new VHDL-based performance modeling capability for multiprocessor systems. The framework for this methodology involved modeling the following system aspects: processor characterization, task modeling, network characterization, and data set size. Initially, all aspects are specified at a high (or abstract) level, and eventually become speci...
متن کاملModeling and Verification of Pipelined Embedded Processors in the Presence of Hazards and Exceptions
Embedded systems present a tremendous opportunity to customize designs by exploiting the application behavior. Due to increasing design complexity deeply pipelined high performance embedded processors are common today. In the presence of hazards and exceptions the validation of pipelined embedded processors is a major challenge. We extend a Finite State Machine (FSM) based modeling of pipelined...
متن کامل